Integrated circuit devices are being fabricated with decreasing transistor geometry sizes that result in increased leakage currents during operation thereof. One solution to reducing leakage currents when operation of the integrated circuit device is not required is to shut down and/or remove power from some or most of the transistor logic circuits of the integrated circuit device. This puts the transistor logic circuits of the integrated circuit device into a “low power mode” that substantially reduces the power requirements of the integrated circuit device during extended standby conditions.
With current architecture implementations of a low power mode in an integrated circuit device, exiting from the low power mode is similar to performing a power-on reset (POR) of the integrated circuit device. While the internal logic states of the integrated circuit device may be woken-up and restored by software and/or firmware, it is important to keep the interaction between the integrated circuit device and other devices in an electronic system that are connected to the integrated circuit device static so as to avoid disturbing the system, and thereby causing unintended actions in and/or by the electronic system.
Through the use of standard input-output (I/O) “keeper” cells, the I/O control and data states of the outputs of the integrated circuit device (during the low power mode) may be retained so as not to upset operation of the other devices in the electronic system. However, upon waking from a low power mode, the I/O control and data states may be reset into a default reset state, e.g., logic 0, logic 1, or unknown, thereby possibly disturbing operation of the other devices in the electronic system. Thus, unintended actions may result to the other devices connected to the integrated circuit device when the integrated circuit device comes out of the low power mode.